1. Field of the Invention
The present invention relates to a motor control circuit and method controlling the rpm of a motor based on digital feedback control.
2. Description of Related Art
As a method of keeping the motor rpm constant, feedback control has been generally used. FIG. 3 is a block diagram of a typical digital feedback control circuit. As shown in FIG. 3, a conventional, typical feedback control circuit 101 includes a comparator 112, a PI (proportional plus integral) arithmetic circuit 113, a constant current circuit/driver 114, a DC motor 115, a detector 116, and a counter 117.
In the digital feedback control circuit 101, the rotation of the DC motor 115 is limited by a current value of the constant current circuit/driver 114, and the detector 116 detects a rotational cycle (period) of the DC motor 115. The counter 117 counts the number of clocks CLK while the detector 116 detects the cycle. Then, the counter sends a count value to the comparator 112. The comparator 112 compares a current speed (motor rpm) sent from the counter 117 with an externally-supplied preset target speed to execute control such that the current speed approximates to the target speed. That is, the arithmetic circuit 113 calculates such a current value as to attain a target speed, and a current value of the constant current circuit/driver 114 is adjusted to drive a motor.
According to such digital feedback control, speed and cycle information are controlled as digital values. Regarding analog feedback control, a resistance or capacitance value should be adjusted in accordance with a load for stable control. In contrast, the digital feedback control has an advantage in that a constant is input as digital data and thus the adjustment is facilitated.
Incidentally, in the feedback circuit, if a target motor rpm is variable, the following problem arises. That is, although a rotational cycle is variable, a counting cycle of the clock CLK is fixed, so an accuracy of adjustment toward the target speed fluctuates. For example, if a counting cycle of clocks to be counted is reduced (frequency is increased) in step with a high rotational speed, a count value increases in the case of driving the motor at low rotational speed. Thus, it is necessary to increase a bit rate of the counter 117. Meanwhile, if a counting cycle of clocks CLK is increased (frequency is decreased) in step with a low rotational speed, a control accuracy upon counting a speed is insufficient in the case of driving the motor at high rotational speed.
Meanwhile, Japanese Unexamined Patent Application Publication No. 2004-54762 (Shoji et al.) discloses a motor controlling apparatus provided with plural counter units and latch units. FIG. 4 is a block diagram of the motor controlling apparatus disclosed by Shoji et al. As shown in FIG. 4, a motor controlling apparatus 200 disclosed by Shoji et al. includes a digital encoder 201, a drive control unit 203, and a motor driver unit 211, and controls driving of a motor 202. The digital encoder 201 outputs a signal of a rectangular waveform each time a mechanism is moved (rotated) by a predetermined distance (angle) as a result of driving the motor 202. The drive control unit 203 includes an LPF (low-pass filter) unit 204, a frequency detecting unit 205, a first speed detecting counter unit 206, a second speed detecting counter unit 207, a first speed information latch unit 208, a second speed information latch unit 209, and a servo control unit 210.
Noise components of an output signal from the digital encoder 201 are removed through the LPF unit 204 of the drive control unit 203, and the resultant signal is input to the frequency detecting unit (edge detecting unit) 205. The frequency detecting unit 205 generates a frequency detection signal based on the output signal of the digital encoder 201 to send the generated signal to the first speed detecting counter unit 206 and the second speed detecting counter unit 207. The two counter units 206 and 207 measure a cycle of the output signal of the digital encoder by counting the number of input clocks. Here, the two counter units differ in terms of a unit encoder cycle. For example, the first speed detecting counter unit 206 counts clocks on the basis of one encoder cycle, and the second speed detecting counter unit 207 counts clocks on the basis of two encoder cycles.
Here, there is an asynchronous relation between an output signal of the digital encoder 201, and the LPF unit 204 and the counter units 206 and 207. As a result, quantization error inevitably occurs. In the case of driving the motor 202 at low rotational speed, a cycle of the output signal of the encoder 201 is long, so an influence of the quantization error is small. However, as the rotational speed increases, the influence of the quantization error becomes larger. As a measure for minimizing the influence of the quantization error upon high-speed rotation, there is a method of increasing a count frequency. However, in this case, the count value increases upon low-speed rotation, so a counter of a high bit rate should be used.
To that end, the counter unit is composed of the two counter units 206 and 207 and the latch units 208 and 209 to overcome the above problem. For example, a reference count value is set to 5 with respect to the target rpm. Even if the motor is actually driven at a speed closer to that speed, a detected count value varies from 4 to 6 (quantization error occurs) in some cases. If one counter is provided, variations of the output count value are not changed (reduced). If two counters are provided, variations of the count value with respect to two encoder cycles are about ½ of variations of the count value with respect to one encoder cycle. Therefore, variations of the count value, that is, quantization error can be suppressed. As described above, in the technique disclosed by Shoji et al., the number of clocks input during plural consecutive cycles is counted to reduce the quantization error.
In the technique disclosed by Shoji et al., plural counter units and latch units are provided, and an influence of the quantization error can be minimized thereby. However, a counting cycle for measuring the motor rpm is fixed, which results in a problem that an accuracy of adjustment toward the target speed is changed between low-speed rotation and high-speed rotation, similar to the aforementioned related art. In other words, if a clock cycle to be counted is reduced in step with a high rotational speed, the count value increases in the case of driving the motor at low speed, so a bit rate of the counter should be increased. Further, there arises another problem in that, if a clock cycle is increased in step with a low rotational speed, a control accuracy is insufficient in the case of driving the motor at high rotational speed.
The above problems are described in detail next. FIGS. 5A, 5B, 6A, and 6B show rotational cycles (cycle of a detection signal D) and clocks CLK upon high-speed rotation and low-speed rotation. For example, if the target rpm of the DC motor is set variable from 10 Hz to 1 kHz, a counter needs to count a cycle longer than 100 ms and count a cycle shorter than 1 ms with sufficient speed detection resolution.
It is assumed that when the rotational speed is high, the cycle is set to, for example, 1 kHz, a bit rate of the counter is 8, and a target speed is about half the maximum count value, that is, 125. In this case, a cycle of the clock CLK is as follows: 1 ms/125=0.008 ms (FIG. 5A). Assuming that a rotational speed is low (10 Hz) with the cycle of the clock CLK, a required bit rate of a counter is about 15 bits (100 ms/0.008 ms=12500) (FIG. 5B). Other circuits should be accordingly configured to set a bit rate with reference to 15 bits (count value), with the result that the circuit scale is increased.
Similarly, considering that a rotational speed is low, for example, 10 Hz, the counting cycle is 100 ms/125=0.8 ms (FIG. 6A). This value is substantially equivalent to 1 bit of the above case where the rotational speed is high (1 kHz=1 ms) (FIG. 6B) The feedback control cannot be executed with sufficient accuracy at this bit rate.